Description
Part Number: DS200UCPBG6AFB
Manufacturer: General Electric
Series: Mark V LM
Product Type: I/O Engine CPU Board
Power Requirements: +5 V dc
Availability: In Stock
Country of Origin: United States
FUNCTIONAL DESCRIPTION:
DS200UCPBG6AFB is an I/O Engine CPU Board manufactured and designed by General Electric as part of the Mark V LM Series used in GE Speedtronic Control Systems. The IO Engine CPU board (UCPB) is the daughterboard mounted on STCA in the IO Engines. The UCPB board contains an 80486DX processor (CPU), a single inline memory module (SIMM) socket with dynamic random access memory (DRAM), flash erasable programmable read-only memory (EPROM) with ROM BIOS, I/O mapped flash EPROM, two RS-232 serial ports, and an ARCNET driver. One UCPB is installed in each of the IO Engines:
The UCPB processor packages the analog and digital IO information and broadcasts it on the COREBUS. The packets are broadcast according to a task schedule. Packets are sets of information grouped according to need and then transmitted for use by other devices. Critical information is broadcast in a fast packet at 100 Hz or every 10 ms, while less critical information is broadcast in ìslow packetsî, which are broadcast at a slower rate than 100 Hz.
UCPB CONFIGURATION:
Hardware: There are three hardware jumpers located on the UCPB board. JP1 and JP3 are used for factory tests. JP2 selects the 486 local bus speed. Initiating a hard re-boot by using the power on/off switch for the specific IO core located in the
Software: The software product for the IO Engine is called TMIA and contains the IO configuration data for the FMVED serial download software, WATT/VAR input, and three pulse rate inputs.
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